1. Field of the Invention
The present invention relates to a Hamming neural network circuit, more particularly, to a programmable and expandable Hamming neural network circuit.
2. Description of Related Art
Currently, an artificial neural network has become a fashionable and popular research topic. The neural network theory is thought to be the technique with the highest potential for solving many artificial intelligence problems. However, because a software neural network cannot satisfy many applications requiring parallel and real-time processing, the design of a very large integrated circuit (VLSI) neural network has become an important research objective.
Referring to FIG. 1, a typical Hamming neural network with a two-layer structure is shown. In a pattern recognition application, the first layer is used to find the matching rates between a to-be-recognized pattern and N standard patterns wherein the boxes on top of the layer are input pixels (11). There are N neurons (12) in the first layer, and each stores a standard pattern. The second layer is a winner-take-all (WTA) network (13) having N inputs and N outputs respectively corresponding to the N inputs. The WTA network (13) is used to find a standard pattern having the maximum matching rate and present a xe2x80x9c1xe2x80x9d on the corresponding output while the other outputs are xe2x80x9c0xe2x80x9ds. Although this typical Hamming neural network is easily constructed, it can only find the standard pattern which is the best match with the to-be-recognized pattern. However, with the rise in system complexity, the increase in the number of standard patterns and especially the development of expanded systems with multiple stages, the above Hamming neural network appears to be unsatisfactory. To enhance system performance, it is necessary to find two or more of the best matched standard patterns for the to-be-recognized pattern. Therefore, a novel Hamming neural network is set forth hereinafter, in which the standard patterns can be output sequentially according the degree to which they match the to-be-recognized pattern. Accordingly, m of the most matched standard patterns can be found sequentially where 1xe2x89xa6mxe2x89xa6N. This will greatly improve the system performance by increasing the recognition rate and reprocessing and reusing data in a multi-stage expanded system.
One object of the present invention is to provide a Hamming neural network circuit which can be programmed to satisfy the requirements in different applications.
Another object of the present invention is to provide a Hamming neural network circuit which can be expanded to enhance its adaptability in various applications.
In accordance with one aspect of the present invention, the Hamming neural network circuit comprises an I/O circuit for inputting and outputting a plurality of standard patterns, a bi-directional transmission gate array connected to the I/O circuit and controlled by a programming signal for transmitting the standard patterns, a plurality of standard pattern memory units connected to the bi-directional transmission gate array for storing the plurality of standard patterns, an address decoder connected to the plurality of standard pattern memory units for addressing one of the plurality of standard pattern memory units, a plurality of pattern matching calculation circuit units respectively connected to the plurality of standard pattern memory units for generating a plurality of matching rates between a to-be-recognized pattern and the plurality of standard patterns, and an expandable matching rate comparing circuit for comparing and sorting the plurality of matching rates.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.